Today in real world the actual application usually needed only a few key features of UART. Specific interface chip will cause of resources and increased cost. In parallel communication the cost as well as complexity of the system increases due to simultaneous transmission of data bits on multiple wires. Serial communication alleviates this drawback of parallel communication and emerges effectively in many applications for long distance communication as it reduces the signal distortion because of its simple structure. This paper focuses on the VHDL implementation of UART with status register which supports asynchronous serial communication. The paper presents the architecture of UART which indicates, during reception of data, parity error, framing error, overrun error and break error using status register. APB is used for solved interfacing problem. With APB other devised are easy to connect with UART. The proposed design of UART satisfies the system requirements of high integration, stabilization, low bit error rate, and low cost. It also supports configurable baud rate generator and variable data length from 5-8 bits per frame. For solving interfacing complexity used an APB.